|Triggers||low, high, don't care|
The small open logic analyzer (sola) is logic analyzer gateware (FPGA firmware) that can be used to turn an FPGA into a logic analyzer, or for analyzing signals internally in an FPGA project like Xilinx's Chipscope. As it's a gateware project that can be used on different FPGA's, the sample speed, number of channels and sample memory is configurable.
Communications between the FPGA and the PC is done via a UART connection at 115200 BAUD. UART to USB conversion depends on FPGA hardware used.
As sola is gateware, it can be used on most FPGA's.
The protocol between the FPGA and the PC is based on the "extended SUMP" protocol with changes to work with more than 32 channels.
The SUMP protocol has short commands, that are exactly one byte long, and long commands, that are 5 bytes long. The long commands's first byte is the opcode, the other 4 bytes are the payload. For example, the Set Trigger Mask command has the opcode 0xC0 and 4 bytes for the trigger values, 1 bit per channel. This approach only works for 32 channels or less.
sola can be configured for 32 or multiples of 32 channels. When configured for more then 32 channels, all long commands are extended. For 64 channels, all long commands are 9 bytes long, for 96, all long commands are 13 bytes long et cetera.
When a command does not need extra bytes for the channels, the extra bytes are set to 0x00.
For example, a long command when configured for 32 channels:
The same command when configured for 64 channels: