CoLA
 | |
| Status | planned |
|---|---|
| Source code | - |
| Channels | 96/48/24 |
| Samplerate | 25MHz/50MHz/100MHz |
| Samplerate (state) | ? |
| Triggers | 32 hardware, 96 bit masked pattern |
| Min/max voltage | 1.65V - 5.5V continuously |
| Threshold voltage | ? |
| Memory | 262144 bytes |
| Compression | RLE, frame omission |
| Website | - |
Introduction
CoLA - Compact Logic Analyzer is an USB3.0 based 96ch/25MHz, 48ch/50MHz or 24ch/100MHz logic analyzer/pattern generator, with built-in hardware pattern triggers, supporting all logic levels from 1.65V to 5.5V. It uses an Intel/Altera Cyclone V FPGA for digital aquisition and FTDI FT601B for 5Gbps USB3.0 support. To limit data transfers, it uses Run Length Encoding (RLE) as well as frame omission. Its compact design and versatility, as well as future upgradability and a DIY approach makes CoLA for an interesting project.
Theory and Design
The aquisition of digital levels are done by an FPGA. The Intel/Altera Cyclone V series have sufficient speed and resources. Although versions with High Speed Serial Interfaces (HSSI's) and an embedded ARM Host Processor System (HPS) exist, a part without these is selected. The 5CEBA5F23C8 has 29.000 ALM / 77.000 LE's and 446 M10K memory blocks of resources. For now, the 150 DSP hardware multiplier modules are not used, but that can change in the future. The FPGA is also equipped with 6 PLL blocks, but only one is used.
To transfer all data to a computer, a part from FTDI is used to communicate over the USB bus. The FT601 has a 5Gbps transceiver, of which 3200Mbps can be used by the chip. The USB chip interfaces to the FPGA by means of a parallel data bus, 32 bits at 100MHz. It uses an external 30MHz crystal to generate all frequencies, and the FPGA inputs the 100MHz clock as its main clock frequency. Apart from the 32 data bits, some other arbitration signals are used.
The 96 inputs/outputs of the CoLA are equipped with logic level translators and diode clamps, to translate and protect from 1.65V to 5.5V, into the 3.3V logic levels that is used inside. The inputs are not isolated and a common ground is used. Data direction can be changed on a per-byte basis.
Inside the FPGA, the logic analyzer parts is divided into three major parts. First, the 96 inputs are routed through a connection matrix-like multiplexer, so every physical input can be routed freely onto every one of the 96 possible input channels. Secondly, the input channels are fed though a framer/packetizer, which outputs frames with a proper preamble and data compression. These frames are stored in a data buffer, ready to transmit. The third and final part is the communication interface with the FT601B chip, that sends data from the buffer and receives configuration information.