sigrok - User contributions [en]

Protocol decoders

2013-09-22T00:32:05Z

Mranostay: /* Possible candidates for future protocol decoders */

This is a list of '''supported protocol decoders (PDs)''' and '''decoders which we might want to write in the future''' (or users might want to contribute).

See [[Protocol decoder API]] for details on how the decoders work in sigrok, and [[Protocol decoder HOWTO]] for a quick introduction about how to write your own decoders.

== Supported protocol decoders ==

Number of currently supported protocol decoders: '''31'''.


Please do '''not''' edit this table in the wiki directly, it is automatically generated.


{| border="0" style="font-size: smaller" class="alternategrey sortable sigroktable"
|-
!Protocol
!Category
!Input IDs
!Output IDs
!Status
!Full name
!Description

{{pd|avr_isp|AVR ISP|AVR in-system programming|Protocol for in-system programming Atmel AVR MCUs.|Flash/debug|spi, logic|avr_isp|supported}}
{{pd|can|CAN|Controller Area Network|Field bus protocol for distributed realtime control.|Automotive|—|can|supported}}
{{pd|dcf77|DCF77|DCF77 time protocol|European longwave time signal (77.5kHz carrier signal).|Time signal|—|dcf77|supported}}
{{pd|ds1307|DS1307|Dallas DS1307|Realtime clock module protocol.|RTC|i2c|ds1307|supported}}
{{pd|edid|EDID|Extended Display Identification Data|Data structure describing display device capabilities.|PC|i2c|edid|supported}}
{{pd|i2cdemux|I2C demux|I2C demultiplexer|Demux I2C packets into per-slave-address streams.|Embedded|i2c|''runtime decision''|supported}}
{{pd|i2cfilter|I2C filter|I2C filter|Filter out addresses/directions in an I2C stream.|Embedded|i2c|i2c|supported}}
{{pd|i2c|I2C|Inter-Integrated Circuit|Two-wire, multi-master, serial bus.|Embedded|—|i2c|supported}}
{{pd|i2s|I2S|Integrated Interchip Sound|Serial bus for connecting digital audio devices.|Audio|—|i2s|supported}}
{{pd|jtag|JTAG|Joint Test Action Group (IEEE 1149.1)|Protocol for testing, debugging, and flashing ICs.|Flash/debug|—|jtag|supported}}
{{pd|jtag_stm32|JTAG / STM32|Joint Test Action Group / ST STM32|ST STM32-specific JTAG protocol.|Flash/debug|jtag|jtag_stm32|supported}}
{{pd|lm75|LM75|National LM75|National LM75 (and compatibles) temperature sensor protocol.|Sensors|i2c|lm75|supported}}
{{pd|lpc|LPC|Low-Pin-Count|Protocol for low-bandwidth devices on PC mainboards.|PC|—|lpc|supported}}
{{pd|maxim_ds28ea00|DS28EA00|Maxim DS28EA00 1-Wire digital thermometer|1-Wire digital thermometer with Sequence Detect and PIO.|Sensors|onewire_network|maxim_ds28ea00|supported}}
{{pd|mlx90614|MLX90614|Melexis MLX90614|Infrared Thermometer protocol.|Sensors|i2c|mlx90614|supported}}
{{pd|mx25lxx05d|MX25Lxx05D|Macronix MX25Lxx05D|SPI (NOR) flash chip protocol.|SPI flash|spi, logic|mx25lxx05d|supported}}
{{pd|mxc6225xu|MXC6225XU|MEMSIC MXC6225XU|Digital Thermal Orientation Sensor (DTOS) protocol.|Sensors|i2c|mxc6225xu|supported}}
{{pd|nunchuk|Nunchuk|Nintendo Wii Nunchuk|Nintendo Wii Nunchuk controller protocol.|Other|i2c|nunchuk|supported}}
{{pd|onewire_link|1-Wire link layer|1-Wire serial communication bus (link layer)|Bidirectional, half-duplex, asynchronous serial bus.|Embedded|—|onewire_link|supported}}
{{pd|onewire_network|1-Wire network layer|1-Wire serial communication bus (network layer)|Bidirectional, half-duplex, asynchronous serial bus.|Embedded|onewire_link|onewire_network|supported}}
{{pd|pan1321|PAN1321|Panasonic PAN1321|Bluetooth RF module with Serial Port Profile (SPP).|Bluetooth|uart|pan1321|supported}}
{{pd|rtc8564|RTC-8564|Epson RTC-8564 JE/NB|Realtime clock module protocol.|RTC|i2c|rtc8564|supported}}
{{pd|sdcard_spi|SD card (SPI mode)|Secure Digital card (SPI mode)|Secure Digital card (SPI mode) low-level protocol.|Memory|spi|sdcard_spi|supported}}
{{pd|spi|SPI|Serial Peripheral Interface|Full-duplex, synchronous, serial bus.|Embedded|—|spi|supported}}
{{pd|tlc5620|TI TLC5620|Texas Instruments TLC5620|Texas Instruments TLC5620 8-bit quad DAC.|DAC|—|tlc5620|supported}}
{{pd|transitioncounter|Transition counter|Pin transition counter|Counts rising/falling edges in the signal.|Other|—|transitioncounter|supported}}
{{pd|uart_dump|UART dump|UART dump|Output decoded UART data to a file.|Embedded|uart|—|supported}}
{{pd|uart|UART|Universal Asynchronous Receiver/Transmitter|Asynchronous, serial bus.|Embedded|—|uart|supported}}
{{pd|usb_protocol|USB protocol|Universal Serial Bus (LS/FS) protocol|USB (low-speed and full-speed) serial protocol.|USB|usb_signalling|usb_protocol|supported}}
{{pd|usb_signalling|USB signalling|Universal Serial Bus (LS/FS) signalling|USB (low-speed and full-speed) signalling protocol.|USB|—|usb_signalling|supported}}v
{{pd|xfp|XFP|10 Gigabit Small Form Factor Pluggable Module (XFP)|Data structure describing device capabilities.|Networking|i2c|xfp|supported}}

|}

== Possible candidates for future protocol decoders ==

{| border="0" style="font-size: smaller" class="alternategrey sortable sigroktable"
|-
!Protocol
!Category
!Input ID(s)
!Output ID(s)
!Status
!Description
!Comments

|-
| SA8807A
| Displays
| spi
|
| bgcolor="red" | 0%
| SPI-attached LCD. Datasheet: [http://pdf1.alldatasheet.com/datasheet-pdf/view/36922/SAMES/SA8807A.html Sames SA8807A].
|

|-
| EA eDIPTFT43-A
| Displays
| i2c
|
| bgcolor="red" | 0%
| I2C-attached LCD. Datasheet: [http://www.lcd-module.de/pdf/grafik/ediptft43-a.pdf EA eDIPTFT43-A].
|

|-
| Analog Devices AD7291
| ADC
| i2c
|
| bgcolor="red" | 0%
| I2C-attached ADC. Datasheet: [http://pdf1.alldatasheet.com/datasheet-pdf/view/318172/AD/AD7291.html Analog Devices AD7291].
|

|-
| Analog Devices ADS1258
| ADC
| spi
| ads1258
| bgcolor="orange" | 10%
| SPI-attached ADC.
| Planned (Uwe Hermann).

|-
| Microchip MCP3901
| ADC
| spi
| mcp3901
| bgcolor="orange" | 10%
| Can be controlled via a parallel protocol, or SPI, or I2C.
| Planned (Uwe Hermann).

|-
| JTAG / TMPA9xx
| Flash/debug
| jtag
| jtag_tmpa9xx
| bgcolor="red" | 0%
| Toshiba TMPA9xx specific JTAG protocol details.
|

|-
| USB / HID
| USB
| usb_protocol
| usb_hid
| bgcolor="red" | 0%
|
|

|-
| USB / USBTMC
| USB
| usb_protocol
| usb_usbtmc
| bgcolor="red" | 0%
|
|

|-
| Dallas DS1985
| Other
| onewire_network
|
| bgcolor="orange" | 10%
| Dallas DS1985 iButton (1-Wire) device.
| Planned (Uwe Hermann).

|-
| Microwire
| Embedded
| —
|
| bgcolor="red" | 0%
|
|

|-
| UNI/O
| Embedded
| —
|
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/Synchronous_Serial_Interface SSI]
| Embedded
| —
|
| bgcolor="red" | 0%
| Synchronous Serial Interface
|

|-
| CompactFlash
| Memory
| —
|
| bgcolor="red" | 0%
|
|

|-
| MMC
| Memory
| —
|
| bgcolor="red" | 0%
|
|

|-
| Memory Stick
| Memory
| —
|
| bgcolor="red" | 0%
|
|

|-
| SmartMedia
| Memory
| —
|
| bgcolor="red" | 0%
|
|

|-
| xD-Picture Card
| Memory
| —
|
| bgcolor="red" | 0%
|
|

|-
| SD card (SD mode)
| Memory
| —
| sdcard_sd
| bgcolor="orange" | 10%
|
| Planned (Uwe Hermann).

|-
| [https://en.wikipedia.org/wiki/ISO/IEC_7816 ISO 7816]
| Smartcards
| —
|
| bgcolor="red" | 0%
|
|

|-
| FlexRay
| Automotive
| —
|
| bgcolor="red" | 0%
| [http://en.wikipedia.org/wiki/Flexray FlexRay] is an automotive network communications protocol.
|

|-
| LIN
| Automotive
| —
|
| bgcolor="red" | 0%
| [http://en.wikipedia.org/wiki/Local_Interconnect_Network LIN] (Local Interconnect Network) is an automotive bus standard.
|

|-
| SWD
| Flash/debug
| —
|
| bgcolor="red" | 0%
| [https://en.wikipedia.org/wiki/Joint_Test_Action_Group#Serial_Wire_Debug Serial Wire Debug]
|

|-
| AVR PDI
| Flash/debug
| —
|
| bgcolor="red" | 0%
| Atmel Program and Debug Interface (PDI) protocol.
|

|-
| AVR TPI
| Flash/debug
| —
|
| bgcolor="red" | 0%
| Atmel Tiny Programming Interface (TPI) protocol.
|

|-
| FWH
| PC
| —
|
| bgcolor="red" | 0%
|
|

|-
| ISA
| PC
| —
|
| bgcolor="red" | 0%
|
|

|-
| PCI
| PC
| —
|
| bgcolor="red" | 0%
|
|

|-
| SMBus
| PC
| —
|
| bgcolor="red" | 0%
|
|

|-
| IDE
| PC
| —
|
| bgcolor="red" | 0%
|
|

|-
| SCSI
| PC
| —
|
| bgcolor="red" | 0%
|
|

|-
| PS/2
| PC
| —
|
| bgcolor="orange" | 10%
|
| Planned (Uwe Hermann).

|-
| [https://en.wikipedia.org/wiki/Platform_Environment_Control_Interface PECI]
| PC
| —
|
| bgcolor="red" | 0%
| Platform Environment Control Interface
|

|-
| [https://en.wikipedia.org/wiki/SVID SVID]
| PC
| —
|
| bgcolor="red" | 0%
| Serial Voltage Identification
|

|-
| AC'97
| Audio
| —
|
| bgcolor="orange" | 10%
|
| Planned (Uwe Hermann).

|-
| MIDI
| Audio
| uart
| midi
| bgcolor="yellow" | 90%
|
| Work in progress (Uwe Hermann).

|-
| HD Audio
| Audio
| —
|
| bgcolor="red" | 0%
|
|

|-
| Nokia NRC17
| IR
| —
|
| bgcolor="red" | 0%
|
|

|-
| Sony SIRC
| IR
| —
|
| bgcolor="red" | 0%
|
|

|-
| Philips RC-5
| IR
| —
|
| bgcolor="red" | 0%
|
|

|-
| Philips RC-6
| IR
| —
|
| bgcolor="red" | 0%
|
|

|-
| Philips RC-MM
| IR
| —
|
| bgcolor="red" | 0%
|
|

|-
| Philips RECS80
| IR
| —
|
| bgcolor="red" | 0%
|
|

|-
| [http://en.wikipedia.org/wiki/Infrared_Data_Association IrDA]
| Misc
| —
|
| bgcolor="red" | 0%
|
|

|-
| PWM
| Misc
| —
|
| bgcolor="red" | 0%
|
|

|-
| AT93C46
| EEPROM
| —
|
| bgcolor="red" | 0%
| Atmel AT93C46 serial EEPROM protocol
|

|-
| HD44780
| Displays
| —
|
| bgcolor="red" | 0%
| [http://en.wikipedia.org/wiki/HD44780_Character_LCD HD44780 character LCD] protocol
|

|-
| 7-segment display
| Displays
| —
|
| bgcolor="red" | 0%
|
|

|-
| [[pcf8814_lcd]]
| Displays
| pcf8814
| pcf8814_lcd
| bgcolor="yellow" | 50%
| Philips PCF8814 65 x 96 pixels matrix LCD driver
| Work in progress (Uwe Hermann).

|-
| GPIB
| Other
| —
| gpib
| bgcolor="orange" | 10%
| [https://en.wikipedia.org/wiki/IEEE-488 General purpose interface bus] (GPIB), a.k.a. IEEE-488.1.
| Planned (Uwe Hermann).

|-
| [https://en.wikipedia.org/wiki/DMX512 DMX512]
| Industrial Lighting
| —
| dmx512
| bgcolor="orange" | 10%
| Digital MultipleX 512
| Planned (Uwe Hermann).

|-
| [https://en.wikipedia.org/wiki/Digital_Signal_Interface DSI]
| Industrial Lighting
| —
| dsi
| bgcolor="red" | 0%
| Digital Serial Interface
|

|-
| [http://en.wikipedia.org/wiki/Digital_Addressable_Lighting_Interface DALI]
| Industrial Lighting
| —
| dali
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/RDM_%28lighting%29 RDM]
| Industrial Lighting
| —
| rdm
| bgcolor="red" | 0%
|
|

|-
| PWM
| Backlight Brightness Control
| —
|
| bgcolor="orange" | 10%
|
| Planned (Matt Ranostay).

|-
| [https://en.wikipedia.org/wiki/NMEA_0183 NMEA 0183]
| GPS
| uart
| nmea0183
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/NMEA_2000 NMEA 2000]
| Marine
| can
| nmea2000
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/Digital_Command_Control DCC]
| Trains
| —
| dcc
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/Train_Communication_Network MVB]
| Trains
| —
|
| bgcolor="red" | 0%
| Multifunction Vehicle Bus
|

|-
| [https://en.wikipedia.org/wiki/Train_Communication_Network WTB]
| Trains
| —
|
| bgcolor="red" | 0%
| Wire Train Bus
|

|-
| [https://en.wikipedia.org/wiki/C-Bus_%28protocol%29 C-Bus]
| Home automation
| —
| cbus
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/X10_%28industry_standard%29 X10]
| Home automation
| —
| x10
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/LonWorks LonWorks]
| Home automation
| —
| lonworks
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/S-Bus S-Bus]
| Home automation
| —
| lonworks
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/Meter-Bus M-Bus]
| Automation
| —
| mbus
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/Modbus Modbus RTU]
| Automation
| uart
| modbus
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/Modbus Modbus ASCII]
| Automation
| uart
| modbus
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/Modbus Modbus TCP]
| Automation
| ip
| modbus
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/Highway_Addressable_Remote_Transducer_Protocol HART protocol]
| Automation
| —
| hart
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/INTERBUS INTERBUS]
| Automation
| —
| interbus
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/DirectNET_Protocol DirectNET]
| Automation
| uart
| directnet
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/KNX_%28standard%29 KNX]
| Automation
| various
| knx
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/Bacnet BACnet]
| Automation
|
| bacnet
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/OpenTherm OpenTherm]
| Automation
| —
| opentherm
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/EBUS_%28serial_buses%29 EBUS]
| Automation
| uart
| ebus
| bgcolor="red" | 0%
|
|

|-
| [https://en.wikipedia.org/wiki/Attachment_Unit_Interface AUI]
| Networking
| —
| aui
| bgcolor="red" | 0%
| Attachment Unit Interface
|

|-
| [https://en.wikipedia.org/wiki/Medium_Dependent_Interface MDI]
| Networking
| —
| mdi
| bgcolor="red" | 0%
| Medium Dependent Interface
|

|-
| [https://en.wikipedia.org/wiki/Media_Independent_Interface MII]
| Networking
| —
| mii
| bgcolor="red" | 0%
| Media Independent Interface
|

|-
| [https://en.wikipedia.org/wiki/Gigabit_Media_Independent_Interface#Gigabit_Media_Independent_Interface GMII]
| Networking
| —
| gmii
| bgcolor="red" | 0%
| Gigabit Media Independent Interface
|

|-
| [https://en.wikipedia.org/wiki/10_Gigabit_Media_Independent_Interface#10_Gigabit_Media_Independent_Interface XGMII]
| Networking
| —
| xgmii
| bgcolor="red" | 0%
| 10 Gigabit Media Independent Interface
|

|-
| [https://en.wikipedia.org/wiki/Management_Data_Input/Output MDIO]
| Networking
| —
| mdio
| bgcolor="red" | 0%
| Management Data Input/Output
|

|-
| [https://en.wikipedia.org/wiki/Wiegand_interface Wiegand]
| RFID
| —
| wiegard
| bgcolor="red" | 0%
| Wiegand interface
|

|}

__FORCETOC__

Openbench Logic Sniffer

2013-09-21T05:57:49Z

Mranostay: /* Known Bugs */

{{Infobox logic analyzer
| image = [[File:Openbench logic sniffer front.png|180px]]
| name = Openbench Logic Sniffer
| status = supported
| source_code_dir = openbench-logic-sniffer
| channels = 32
| samplerate = 200MHz
| samplerate_state = ?
| triggers = ?
| voltages = ?
| memory = 24ksamples
| compression = RLE (optional)
| website = [http://dangerousprototypes.com/docs/Open_Bench_Logic_Sniffer dangerousprototypes.com]
}}

The '''Openbench Logic Sniffer (OLS)''' is an FPGA-based logic analyzer, supporting 32 probes for probing up to 100MHz signals and advanced trigger functionality. It is a fully open source device — the circuit design, VHDL code for the FPGA, firmware for the PIC microcontroller and Java-based client software are all freely available. The project is a collaboration between [http://www.gadgetfactory.net/ Gadget Factory] and [http://dangerousprototypes.com/ Dangerous Prototypes].

The device started life as the [http://www.sump.org/projects/analyzer/ Sump Logic Analyzer], which was meant to be run on a Digilent FPGA development board. The Openbench Logic Analyzer unit is a custom-designed board with low cost in mind: it can be bought for $45 from [http://www.seeedstudio.com/depot/preorder-open-workbench-logic-sniffer-p-612.html?cPath=61_76 Seeed Studio].

Communication between the board and the PC is done via a USB port connected to a PIC 18F24J50 microcontroller, which presents a standard USB ACM profile. The host handles this as a serial port. The default maximum serial speed of the SUMP Java client is 115200bps, but the USB ACM virtual serial port can be opened at much higher speeds. An overview of the endpoint profile is at [[Openbench Logic Sniffer/Info]].

Full OLS info: [http://dangerousprototypes.com/docs/Open_Bench_Logic_Sniffer dangerousprototypes.com: Open Bench Logic Sniffer]

'''Status:'''

The sigrok driver does not currently support the "serial" trigger mode. This allows a single trigger to be set (on one or more probes), but with up to 32 stages. The parallel mode is supported, which supports up to 4 distinct trigger stages on any probe.

200MHz demux mode will not work right now, since the driver always expects 32-bit sample values.

== Hardware ==

* Xilinx Spartan XC3S250E
* Microchip PIC18F24J50-I/30
* Atmel 0952 450B0410 SU
* ON Semiconductor LCX16245

== Photos ==

<gallery>
File:Openbench logic sniffer front.jpg|Device, front
File:Openbench logic sniffer back.jpg|Device, back
File:Ols buffer.png|Device with buffer "wing"
</gallery>

== Protocol ==

The communications protocol between the board and the PC is below, taken from the [http://www.sump.org/projects/analyzer/protocol/ original Sump documentation].

All communication is done using a standard RS232 connection with 8 data bits, 1 stop bit and no parity. The transfer rate is not emulated over USB and can be set to any speed supported by the operating system. Pump-loader, an update utility for the Logic Sniffer ROM chip, uses 921600bps by default. XON/XOFF software flow control is available.

When sending captured data the analyzer will send blocks of four bytes, the first containing the lowest channels. No start or end sequence exists. The host can assume an end of transmission if no data has been received for the duration of one byte.

The protocol used by hardware version 0.5 and older is not covered here. Hardware 0.6 uses protocol version 0, and hardware 0.7 uses protocol version 1. Unless otherwise stated, commands exist in both versions.

The following list provides a short overview of commands understood by the analyzer.

=== Short Commands ===

These commands are exactly one byte long.

'''Reset (0x00)'''
: Resets the device. Should be sent 5 times when the receiver status is unknown. (It could be waiting for up to four bytes of pending long command data.)

'''Run (0x01)'''
: Arms the trigger.

'''ID (0x02)'''
: Asks for device identification. The device will respond with four bytes. The first three ("SLA") identify the device. The last one identifies the protocol version which is currently either "0" or "1".

'''XON (0x11)'''
: Put transmitter out of pause mode. It will continue to transmit captured data if any is pending. This command is being used for xon/xoff flow control.

'''XOFF (0x13)'''
: Put transmitter in pause mode. It will stop transmitting captured data. This command is being used for xon/xoff flow control.

=== Long Commands ===

Are five bytes long. The first byte contains the opcode. The bytes are displayed in the order in which they are sent to the serial port starting left. The bits within one byte are displayed most significant first.

'''Set Trigger Mask (0xc0, 0xc4, 0xc8, 0xcc)'''
: Defines which trigger values must match. In parallel mode each bit represents one channel, in serial mode each bit represents one of the last 32 samples of the selected channel. The opcodes refer to stage 0-3 in the order given above. (Protocol version 0 only supports stage 0.)
: [[Image:1100xx00.png]]

'''Set Trigger Values (0xc1, 0xc5, 0xc9, 0xcd)'''
: Defines which values individual bits must have. In parallel mode each bit represents one channel, in serial mode each bit represents one of the last 32 samples of the selected channel. The opcodes refer to stage 0-3 in the order given above. (Protocol version 0 only supports stage 0.)
: [[Image:1100xx01.png]]

'''Set Trigger Configuration (0xc2, 0xc6, 0xca, 0xce)'''
: Configures the selected trigger stage. The opcodes refer to stage 0-3 in the order given above. The following parameters will be set:

:: '''delay'''
::: If a match occures, the action of the stage is delayed by the given number of samples.
:: '''level'''
::: Trigger level at which the stage becomes active.
:: '''channel'''
::: Channel to be used in serial mode. (0-31 in normal operation; 0-15 when demux flag is set)
:: '''serial'''
::: When set to 1 the stage operates as serial trigger, otherwise it used as parallel trigger.
:: '''start'''
::: When set to 1 a match will start the capturing process. The trigger level will rise on match regardless of this flag. (Command available as of protocol version 1.)

: [[Image:1100xx10.png]]

'''Set Divider (0x80)'''
: When x is written, the sampling frequency is set to f = clock / (x + 1).

: [[Image:10000000.png]]

'''Set Read & Delay Count (0x81)'''
: Read Count is the number of samples (divided by four) to read back from memory and sent to the host computer. Delay Count is the number of samples (divided by four) to capture after the trigger fired. A Read Count bigger than the Delay Count means that data from before the trigger match will be read back. This data will only be valid if the device was running long enough before the trigger matched.
: [[Image:10000001.png]]

'''Set Flags (0x82)'''
: Sets the following flags:

:: '''demux'''
::: Enables the demux input module. (Filter must be off.)
:: '''filter'''
::: Enables the filter input module. (Demux must be off.)
:: '''channel groups'''
::: Disable channel group. Disabled groups are excluded from data transmissions. This can be used to speed up transfers. There are four groups, each represented by one bit. Starting with the least significant bit of the channel group field channels are assigned as follows: 0-7, 8-15, 16-23, 24-31.
:: '''external'''
::: Selects the clock to be used for sampling. If set to 0, the internal clock divided by the configured divider is used, and if set to 1, the external clock will be used. Filter and demux are only available with internal clock.
:: '''inverted'''
::: When set to 1, the external clock will be inverted before being used. The inversion causes a delay that may cause problems at very high clock rates. This option only has an effect with external set to 1.

: [[Image:10000010.png]]

=== Known Bugs ===

RLE mode is currently broken due to samples count being passed in from sigrok is the total samples we will receive, but however the OLS sees this as compressed samples so in turn we can never know how many samples will get send back. Even worse since the buffer is sent backwards you are likely to lose all the data you are trying to trace at the beginning of the session.

== Resources ==

* [http://dangerousprototypes.com/docs/Open_Bench_Logic_Sniffer Open Bench Logic Sniffer] (main wiki page)
* [http://dangerousprototypes.com/docs/Logic_Sniffer_upgrade_procedure Logic Sniffer upgrade procedure]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Supported]]
[[Category:Sump protocol]]

Openbench Logic Sniffer

2013-09-21T05:57:22Z

Mranostay:

{{Infobox logic analyzer
| image = [[File:Openbench logic sniffer front.png|180px]]
| name = Openbench Logic Sniffer
| status = supported
| source_code_dir = openbench-logic-sniffer
| channels = 32
| samplerate = 200MHz
| samplerate_state = ?
| triggers = ?
| voltages = ?
| memory = 24ksamples
| compression = RLE (optional)
| website = [http://dangerousprototypes.com/docs/Open_Bench_Logic_Sniffer dangerousprototypes.com]
}}

The '''Openbench Logic Sniffer (OLS)''' is an FPGA-based logic analyzer, supporting 32 probes for probing up to 100MHz signals and advanced trigger functionality. It is a fully open source device — the circuit design, VHDL code for the FPGA, firmware for the PIC microcontroller and Java-based client software are all freely available. The project is a collaboration between [http://www.gadgetfactory.net/ Gadget Factory] and [http://dangerousprototypes.com/ Dangerous Prototypes].

The device started life as the [http://www.sump.org/projects/analyzer/ Sump Logic Analyzer], which was meant to be run on a Digilent FPGA development board. The Openbench Logic Analyzer unit is a custom-designed board with low cost in mind: it can be bought for $45 from [http://www.seeedstudio.com/depot/preorder-open-workbench-logic-sniffer-p-612.html?cPath=61_76 Seeed Studio].

Communication between the board and the PC is done via a USB port connected to a PIC 18F24J50 microcontroller, which presents a standard USB ACM profile. The host handles this as a serial port. The default maximum serial speed of the SUMP Java client is 115200bps, but the USB ACM virtual serial port can be opened at much higher speeds. An overview of the endpoint profile is at [[Openbench Logic Sniffer/Info]].

Full OLS info: [http://dangerousprototypes.com/docs/Open_Bench_Logic_Sniffer dangerousprototypes.com: Open Bench Logic Sniffer]

'''Status:'''

The sigrok driver does not currently support the "serial" trigger mode. This allows a single trigger to be set (on one or more probes), but with up to 32 stages. The parallel mode is supported, which supports up to 4 distinct trigger stages on any probe.

200MHz demux mode will not work right now, since the driver always expects 32-bit sample values.

== Hardware ==

* Xilinx Spartan XC3S250E
* Microchip PIC18F24J50-I/30
* Atmel 0952 450B0410 SU
* ON Semiconductor LCX16245

== Photos ==

<gallery>
File:Openbench logic sniffer front.jpg|Device, front
File:Openbench logic sniffer back.jpg|Device, back
File:Ols buffer.png|Device with buffer "wing"
</gallery>

== Protocol ==

The communications protocol between the board and the PC is below, taken from the [http://www.sump.org/projects/analyzer/protocol/ original Sump documentation].

All communication is done using a standard RS232 connection with 8 data bits, 1 stop bit and no parity. The transfer rate is not emulated over USB and can be set to any speed supported by the operating system. Pump-loader, an update utility for the Logic Sniffer ROM chip, uses 921600bps by default. XON/XOFF software flow control is available.

When sending captured data the analyzer will send blocks of four bytes, the first containing the lowest channels. No start or end sequence exists. The host can assume an end of transmission if no data has been received for the duration of one byte.

The protocol used by hardware version 0.5 and older is not covered here. Hardware 0.6 uses protocol version 0, and hardware 0.7 uses protocol version 1. Unless otherwise stated, commands exist in both versions.

The following list provides a short overview of commands understood by the analyzer.

=== Short Commands ===

These commands are exactly one byte long.

'''Reset (0x00)'''
: Resets the device. Should be sent 5 times when the receiver status is unknown. (It could be waiting for up to four bytes of pending long command data.)

'''Run (0x01)'''
: Arms the trigger.

'''ID (0x02)'''
: Asks for device identification. The device will respond with four bytes. The first three ("SLA") identify the device. The last one identifies the protocol version which is currently either "0" or "1".

'''XON (0x11)'''
: Put transmitter out of pause mode. It will continue to transmit captured data if any is pending. This command is being used for xon/xoff flow control.

'''XOFF (0x13)'''
: Put transmitter in pause mode. It will stop transmitting captured data. This command is being used for xon/xoff flow control.

=== Long Commands ===

Are five bytes long. The first byte contains the opcode. The bytes are displayed in the order in which they are sent to the serial port starting left. The bits within one byte are displayed most significant first.

'''Set Trigger Mask (0xc0, 0xc4, 0xc8, 0xcc)'''
: Defines which trigger values must match. In parallel mode each bit represents one channel, in serial mode each bit represents one of the last 32 samples of the selected channel. The opcodes refer to stage 0-3 in the order given above. (Protocol version 0 only supports stage 0.)
: [[Image:1100xx00.png]]

'''Set Trigger Values (0xc1, 0xc5, 0xc9, 0xcd)'''
: Defines which values individual bits must have. In parallel mode each bit represents one channel, in serial mode each bit represents one of the last 32 samples of the selected channel. The opcodes refer to stage 0-3 in the order given above. (Protocol version 0 only supports stage 0.)
: [[Image:1100xx01.png]]

'''Set Trigger Configuration (0xc2, 0xc6, 0xca, 0xce)'''
: Configures the selected trigger stage. The opcodes refer to stage 0-3 in the order given above. The following parameters will be set:

:: '''delay'''
::: If a match occures, the action of the stage is delayed by the given number of samples.
:: '''level'''
::: Trigger level at which the stage becomes active.
:: '''channel'''
::: Channel to be used in serial mode. (0-31 in normal operation; 0-15 when demux flag is set)
:: '''serial'''
::: When set to 1 the stage operates as serial trigger, otherwise it used as parallel trigger.
:: '''start'''
::: When set to 1 a match will start the capturing process. The trigger level will rise on match regardless of this flag. (Command available as of protocol version 1.)

: [[Image:1100xx10.png]]

'''Set Divider (0x80)'''
: When x is written, the sampling frequency is set to f = clock / (x + 1).

: [[Image:10000000.png]]

'''Set Read & Delay Count (0x81)'''
: Read Count is the number of samples (divided by four) to read back from memory and sent to the host computer. Delay Count is the number of samples (divided by four) to capture after the trigger fired. A Read Count bigger than the Delay Count means that data from before the trigger match will be read back. This data will only be valid if the device was running long enough before the trigger matched.
: [[Image:10000001.png]]

'''Set Flags (0x82)'''
: Sets the following flags:

:: '''demux'''
::: Enables the demux input module. (Filter must be off.)
:: '''filter'''
::: Enables the filter input module. (Demux must be off.)
:: '''channel groups'''
::: Disable channel group. Disabled groups are excluded from data transmissions. This can be used to speed up transfers. There are four groups, each represented by one bit. Starting with the least significant bit of the channel group field channels are assigned as follows: 0-7, 8-15, 16-23, 24-31.
:: '''external'''
::: Selects the clock to be used for sampling. If set to 0, the internal clock divided by the configured divider is used, and if set to 1, the external clock will be used. Filter and demux are only available with internal clock.
:: '''inverted'''
::: When set to 1, the external clock will be inverted before being used. The inversion causes a delay that may cause problems at very high clock rates. This option only has an effect with external set to 1.

: [[Image:10000010.png]]

=== Known Bugs ===

RLE mode is currently broken due to samples count being passed in from sigrok is the total samples we will receive, but however the OLS sees this as compressed samples so in turn we can never know how many samples will get send back. And since the buffer is sent backwards you are likely to lose all the data you are trying to trace at the beginning of the session.

== Resources ==

* [http://dangerousprototypes.com/docs/Open_Bench_Logic_Sniffer Open Bench Logic Sniffer] (main wiki page)
* [http://dangerousprototypes.com/docs/Logic_Sniffer_upgrade_procedure Logic Sniffer upgrade procedure]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Supported]]
[[Category:Sump protocol]]

Openbench Logic Sniffer

2013-09-21T05:57:00Z

Mranostay:

{{Infobox logic analyzer
| image = [[File:Openbench logic sniffer front.png|180px]]
| name = Openbench Logic Sniffer
| status = supported
| source_code_dir = openbench-logic-sniffer
| channels = 32
| samplerate = 200MHz
| samplerate_state = ?
| triggers = ?
| voltages = ?
| memory = 24ksamples
| compression = RLE (optional)
| website = [http://dangerousprototypes.com/docs/Open_Bench_Logic_Sniffer dangerousprototypes.com]
}}

The '''Openbench Logic Sniffer (OLS)''' is an FPGA-based logic analyzer, supporting 32 probes for probing up to 100MHz signals and advanced trigger functionality. It is a fully open source device — the circuit design, VHDL code for the FPGA, firmware for the PIC microcontroller and Java-based client software are all freely available. The project is a collaboration between [http://www.gadgetfactory.net/ Gadget Factory] and [http://dangerousprototypes.com/ Dangerous Prototypes].

The device started life as the [http://www.sump.org/projects/analyzer/ Sump Logic Analyzer], which was meant to be run on a Digilent FPGA development board. The Openbench Logic Analyzer unit is a custom-designed board with low cost in mind: it can be bought for $45 from [http://www.seeedstudio.com/depot/preorder-open-workbench-logic-sniffer-p-612.html?cPath=61_76 Seeed Studio].

Communication between the board and the PC is done via a USB port connected to a PIC 18F24J50 microcontroller, which presents a standard USB ACM profile. The host handles this as a serial port. The default maximum serial speed of the SUMP Java client is 115200bps, but the USB ACM virtual serial port can be opened at much higher speeds. An overview of the endpoint profile is at [[Openbench Logic Sniffer/Info]].

Full OLS info: [http://dangerousprototypes.com/docs/Open_Bench_Logic_Sniffer dangerousprototypes.com: Open Bench Logic Sniffer]

'''Status:'''

The sigrok driver does not currently support the "serial" trigger mode. This allows a single trigger to be set (on one or more probes), but with up to 32 stages. The parallel mode is supported, which supports up to 4 distinct trigger stages on any probe.

200MHz demux mode will not work right now, since the driver always expects 32-bit sample values.

== Hardware ==

* Xilinx Spartan XC3S250E
* Microchip PIC18F24J50-I/30
* Atmel 0952 450B0410 SU
* ON Semiconductor LCX16245

== Photos ==

<gallery>
File:Openbench logic sniffer front.jpg|Device, front
File:Openbench logic sniffer back.jpg|Device, back
File:Ols buffer.png|Device with buffer "wing"
</gallery>

== Protocol ==

The communications protocol between the board and the PC is below, taken from the [http://www.sump.org/projects/analyzer/protocol/ original Sump documentation].

All communication is done using a standard RS232 connection with 8 data bits, 1 stop bit and no parity. The transfer rate is not emulated over USB and can be set to any speed supported by the operating system. Pump-loader, an update utility for the Logic Sniffer ROM chip, uses 921600bps by default. XON/XOFF software flow control is available.

When sending captured data the analyzer will send blocks of four bytes, the first containing the lowest channels. No start or end sequence exists. The host can assume an end of transmission if no data has been received for the duration of one byte.

The protocol used by hardware version 0.5 and older is not covered here. Hardware 0.6 uses protocol version 0, and hardware 0.7 uses protocol version 1. Unless otherwise stated, commands exist in both versions.

The following list provides a short overview of commands understood by the analyzer.

=== Short Commands ===

These commands are exactly one byte long.

'''Reset (0x00)'''
: Resets the device. Should be sent 5 times when the receiver status is unknown. (It could be waiting for up to four bytes of pending long command data.)

'''Run (0x01)'''
: Arms the trigger.

'''ID (0x02)'''
: Asks for device identification. The device will respond with four bytes. The first three ("SLA") identify the device. The last one identifies the protocol version which is currently either "0" or "1".

'''XON (0x11)'''
: Put transmitter out of pause mode. It will continue to transmit captured data if any is pending. This command is being used for xon/xoff flow control.

'''XOFF (0x13)'''
: Put transmitter in pause mode. It will stop transmitting captured data. This command is being used for xon/xoff flow control.

=== Long Commands ===

Are five bytes long. The first byte contains the opcode. The bytes are displayed in the order in which they are sent to the serial port starting left. The bits within one byte are displayed most significant first.

'''Set Trigger Mask (0xc0, 0xc4, 0xc8, 0xcc)'''
: Defines which trigger values must match. In parallel mode each bit represents one channel, in serial mode each bit represents one of the last 32 samples of the selected channel. The opcodes refer to stage 0-3 in the order given above. (Protocol version 0 only supports stage 0.)
: [[Image:1100xx00.png]]

'''Set Trigger Values (0xc1, 0xc5, 0xc9, 0xcd)'''
: Defines which values individual bits must have. In parallel mode each bit represents one channel, in serial mode each bit represents one of the last 32 samples of the selected channel. The opcodes refer to stage 0-3 in the order given above. (Protocol version 0 only supports stage 0.)
: [[Image:1100xx01.png]]

'''Set Trigger Configuration (0xc2, 0xc6, 0xca, 0xce)'''
: Configures the selected trigger stage. The opcodes refer to stage 0-3 in the order given above. The following parameters will be set:

:: '''delay'''
::: If a match occures, the action of the stage is delayed by the given number of samples.
:: '''level'''
::: Trigger level at which the stage becomes active.
:: '''channel'''
::: Channel to be used in serial mode. (0-31 in normal operation; 0-15 when demux flag is set)
:: '''serial'''
::: When set to 1 the stage operates as serial trigger, otherwise it used as parallel trigger.
:: '''start'''
::: When set to 1 a match will start the capturing process. The trigger level will rise on match regardless of this flag. (Command available as of protocol version 1.)

: [[Image:1100xx10.png]]

'''Set Divider (0x80)'''
: When x is written, the sampling frequency is set to f = clock / (x + 1).

: [[Image:10000000.png]]

'''Set Read & Delay Count (0x81)'''
: Read Count is the number of samples (divided by four) to read back from memory and sent to the host computer. Delay Count is the number of samples (divided by four) to capture after the trigger fired. A Read Count bigger than the Delay Count means that data from before the trigger match will be read back. This data will only be valid if the device was running long enough before the trigger matched.
: [[Image:10000001.png]]

'''Set Flags (0x82)'''
: Sets the following flags:

:: '''demux'''
::: Enables the demux input module. (Filter must be off.)
:: '''filter'''
::: Enables the filter input module. (Demux must be off.)
:: '''channel groups'''
::: Disable channel group. Disabled groups are excluded from data transmissions. This can be used to speed up transfers. There are four groups, each represented by one bit. Starting with the least significant bit of the channel group field channels are assigned as follows: 0-7, 8-15, 16-23, 24-31.
:: '''external'''
::: Selects the clock to be used for sampling. If set to 0, the internal clock divided by the configured divider is used, and if set to 1, the external clock will be used. Filter and demux are only available with internal clock.
:: '''inverted'''
::: When set to 1, the external clock will be inverted before being used. The inversion causes a delay that may cause problems at very high clock rates. This option only has an effect with external set to 1.

: [[Image:10000010.png]]

==- Known Bugs ===

RLE mode is currently broken due to samples count being passed in from sigrok is the total samples we will receive, but however the OLS sees this as compressed samples so in turn we can never know how many samples will get send back. And since the buffer is sent backwards you are likely to lose all the data you are trying to trace at the beginning of the session.

== Resources ==

* [http://dangerousprototypes.com/docs/Open_Bench_Logic_Sniffer Open Bench Logic Sniffer] (main wiki page)
* [http://dangerousprototypes.com/docs/Logic_Sniffer_upgrade_procedure Logic Sniffer upgrade procedure]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Supported]]
[[Category:Sump protocol]]

Protocol decoders

2013-04-03T07:32:25Z

Mranostay: /* Possible candidates for future protocol decoders */

Protocol decoders

2013-04-03T07:31:36Z

Mranostay: /* Possible candidates for future protocol decoders */

Protocol decoders

2013-03-11T21:43:32Z

Mranostay: /* Possible candidates for future protocol decoders */

Protocol decoders

2013-02-28T00:20:47Z

Mranostay: