Saleae Logic16

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Revision as of 20:37, 28 July 2013 by Uwe Hermann (talk | contribs) (→‎Hardware: Testpoints.)
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Saleae Logic16
Saleae Logic16.jpg
Status planned
Channels 2/4/8/16
Samplerate 100/50/25/12.5MHz
Samplerate (state)
Triggers none (SW-only)
Min/max voltage -0.9V — 6V
Threshold voltage configurable:
for 1.8V to 3.6V systems: VIH=1.4V, VIL=0.7V
for 5V systems: VIH=3.6V, VIL=1.4V
Memory none
Compression yes
Website saleae.com

The Saleae Logic16 is a USB-based, 16-channel logic analyzer with 100/50/25/12.5MHz sampling rate (at 2/4/8/16 enabled channels).

The case requires a Torx T5 screwdriver to open.

See Saleae Logic16/Info for more details (such as lsusb -vvv output) about the device.

See Saleae Logic for the predecessor product of the Saleae Logic16.

Hardware

Pinouts and connections:

JTAG header (FPGA):

The J3 pin header is a JTAG connector wired to the FPGA. The pins are (from left to right):

1 2 3 4 5
GND TMS TCK TDO TDI

Testpoints:

T1 T2 T3
1.2V 3.3V GND (FX2)

Photos

Firmware

The firmware for the FX2LP is embedded in the vendor application as a set of Intel HEX lines. Each line is uploaded individually with a separate control transfer. The firmware currently occupies the address range [0x0000-0x145d], but is uploaded out of order. TODO: Make a tool to extract the firmware from the application binary.

See Saleae Logic16/Firmware for more details on the vendor firmware.

Protocol

Sample format:

The samples (as received via USB) for the enabled probes (3, 6, 9, or 16) are organized as follows:

0xLL 0xLL  0xMM 0xMM  0xNN 0xNN   0xPP 0xPP  0xQQ 0xQQ  0xRR 0xRR ...

In the above example, 3 probes are enabled. For each probe there are 2 bytes / 16 bits (e.g. 0xLL 0xLL for probe 0), then the next probe's data is received (0xMM 0xMM for probe 1), then 0xNN 0xNN for probe 2. When 2 bytes have been received for all enabled probes, the process restarts with probe 0 again.

The 16 bits of data per probe seem to contain the pin state of the respective probe (1: high, 0: low) at 16 different sampling points/times (which ones depends on the samplerate).

Configuration:

Endpoint 1 is used for configuration of the analyzer. The transfers are "encrypted" using a simple series of additions and XORs. Two kinds of transfers are used; a 3 byte out transfer starting with 0x81 followed by a 1 byte in transfer, and a 4 byte out transfer starting with 0x80. It's quite plausible that these provide raw read/write access to memory locations.

Channel number configuration
3 channels 0x80 0x01 0x02 0x07 0x80 0x01 0x03 0x00
6 channels 0x80 0x01 0x02 0x3f 0x80 0x01 0x03 0x00
9 channels 0x80 0x01 0x02 0xff 0x80 0x01 0x03 0x01
16 channels 0x80 0x01 0x02 0xff 0x80 0x01 0x03 0xff
Sampling frequency
500 kHz 0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0xc7
1 MHz 0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x63
2 MHz 0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x31
4 MHz 0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x18
5 MHz 0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x13
8 MHz 0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x13
10 MHz 0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x09
12.5 MHz 0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x07
16 MHz 0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x09
25 MHz 0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x03
32 MHz 0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x04
40 MHz 0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x03
50 MHz 0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x01
80 MHz 0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x01
100 MHz 0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x00

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