sigrok - User contributions [en]

Talk:Dangerous Prototypes Buspirate

2010-05-26T11:28:35Z

Ian: /* Generic SUMP Client Support? */

== Generic SUMP Client Support? ==

The bus pirate logic analyzer mode implements the [http://www.sump.org/projects/analyzer/protocol/ SUMP protocol] in order work with the [http://www.sump.org/projects/analyzer/client/ SUMP logic analyzer client]. I believe the other devices from [http://dangerousprototypes.com/ Dangerous Prototypes], namely the [http://dangerousprototypes.com/open-logic-sniffer/ Open Logic Sniffer] and even the tiny [http://dangerousprototypes.com/usb-ir-toy-manual/ USB IR Toy] implement the SUMP protocol.

So will Sigrok implement the SUMP protocol somewhat generically and be able to work with devices that speak it?

[[User:Rct|Rct]] 15:37, 22 April 2010 (UTC)

: Hi, and welcome! Yes, we do already have partial support for the OpenBench Logic Sniffer (thus we indeed support the SUMP protocol). Not sure about the USB IR Toy (I don't think any of the developers has one, or at least not yet), but we'll have multiple OpenBench Logic Sniffers and at least one Buspirate soonish and we'll definately support them!
--[[User:Uwe Hermann|Uwe Hermann]] 21:33, 22 April 2010 (UTC)

: The Logic Sniffer, Bus Pirate, and USB IR Toy all implement a SUMP protocol compatible interface. Support for one enables support for all of them, protocol-wise. The Bus Pirate and IR Toy ignore lots of settings though, but they're still 100% compatible with SUMP. They're all implemented over a serial port too, there's no difference in communicating with them.
--[[User:Ian|Ian]] 11:27, 26 May 2010 (UTC)

Talk:Dangerous Prototypes Buspirate

2010-05-26T11:27:35Z

Ian: /* Generic SUMP Client Support? */

Talk:Dangerous Prototypes Buspirate

2010-05-26T11:27:19Z

Ian: /* Generic SUMP Client Support? */

Talk:Dangerous Prototypes Buspirate

2010-05-26T11:26:57Z

Ian: /* Generic SUMP Client Support? */

== Generic SUMP Client Support? ==

The bus pirate logic analyzer mode implements the [http://www.sump.org/projects/analyzer/protocol/ SUMP protocol] in order work with the [http://www.sump.org/projects/analyzer/client/ SUMP logic analyzer client]. I believe the other devices from [http://dangerousprototypes.com/ Dangerous Prototypes], namely the [http://dangerousprototypes.com/open-logic-sniffer/ Open Logic Sniffer] and even the tiny [http://dangerousprototypes.com/usb-ir-toy-manual/ USB IR Toy] implement the SUMP protocol.

So will Sigrok implement the SUMP protocol somewhat generically and be able to work with devices that speak it?

[[User:Rct|Rct]] 15:37, 22 April 2010 (UTC)

: Hi, and welcome! Yes, we do already have partial support for the OpenBench Logic Sniffer (thus we indeed support the SUMP protocol). Not sure about the USB IR Toy (I don't think any of the developers has one, or at least not yet), but we'll have multiple OpenBench Logic Sniffers and at least one Buspirate soonish and we'll definately support them! --[[User:Uwe Hermann|Uwe Hermann]] 21:33, 22 April 2010 (UTC)

: The Logic Sniffer, Bus Pirate, and USB IR Toy all implement a SUMP protocol compatible interface. Support for one enables support for all of them, protocol-wise. The Bus Pirate and IR Toy ignore lots of settings though, but they're still 100% compatible with SUMP.
--[[User:Ian|Ian]] 11:26, 26 May 2010 (UTC)[[User:Ian|Ian]] 15:37, 26 May 2010 (UTC):

Talk:Dangerous Prototypes Buspirate

2010-05-26T11:26:45Z

Ian: /* Generic SUMP Client Support? */

== Generic SUMP Client Support? ==

The bus pirate logic analyzer mode implements the [http://www.sump.org/projects/analyzer/protocol/ SUMP protocol] in order work with the [http://www.sump.org/projects/analyzer/client/ SUMP logic analyzer client]. I believe the other devices from [http://dangerousprototypes.com/ Dangerous Prototypes], namely the [http://dangerousprototypes.com/open-logic-sniffer/ Open Logic Sniffer] and even the tiny [http://dangerousprototypes.com/usb-ir-toy-manual/ USB IR Toy] implement the SUMP protocol.

So will Sigrok implement the SUMP protocol somewhat generically and be able to work with devices that speak it?

[[User:Rct|Rct]] 15:37, 22 April 2010 (UTC)

: Hi, and welcome! Yes, we do already have partial support for the OpenBench Logic Sniffer (thus we indeed support the SUMP protocol). Not sure about the USB IR Toy (I don't think any of the developers has one, or at least not yet), but we'll have multiple OpenBench Logic Sniffers and at least one Buspirate soonish and we'll definately support them! --[[User:Uwe Hermann|Uwe Hermann]] 21:33, 22 April 2010 (UTC)

The Logic Sniffer, Bus Pirate, and USB IR Toy all implement a SUMP protocol compatible interface. Support for one enables support for all of them, protocol-wise. The Bus Pirate and IR Toy ignore lots of settings though, but they're still 100% compatible with SUMP.
--[[User:Ian|Ian]] 11:26, 26 May 2010 (UTC)[[User:Ian|Ian]] 15:37, 26 May 2010 (UTC):

Logic analyzer comparison

2010-05-26T08:41:22Z

Ian:

This is an alphabetically ordered table of various logic analyzer products (commercial and non-commercial) with a short overview of their capabilities. We list all kinds of devices here, not only those supported by sigrok.

You should '''not''' use the information here as the sole source for any buying decisions, this is just meant for informational purposes. Please carefully check the vendor websites if you intend to buy any hardware.

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
!Logic analyzer
!Channels
!Samplerates/MHz
!Voltages/V
!Architecture/chip
!Memory
!Compression
!Vendor software
!Protocol decoders
!Price

|- bgcolor="#6699ff"
| colspan="10" | '''Commercial'''

|- bgcolor="#eeeeee"
| [[ASIX SIGMA]]
| 4/8/16
| 200/100/50
| TTL1
| Spartan-3 + SDRAM
| 256Mbit (56/28/14Msmp/ch)
| RLE
|
| I2C, SPI, UART
| €298.-

|- bgcolor="#dddddd"
| [[Braintechnology USB-LPS]]
| 8/16
| 0.12-24/0.12-122
| 3.3/5
| Cypress FX2
| none
| none
| Windows
| I2C, SPI, UART
| €129.-

|- bgcolor="#eeeeee"
| [[CWAV USBee SX]]
| 8
| 1-24
|
| Cypress FX2
| none
| none
| Windows
| I2C, SPI, UART
| $139.-

|- bgcolor="#dddddd"
| [[Intronix Logicport]]
| 34
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://www.inovaflex.de/logicmaid.html Inovaflex LogicMaid]
|
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://www.nci-usa.com/frame_products_overview.htm NCI GoLogic] (various)
| 36/72
| 250,500 w/o RLE
| cfg.
| Virtex-II + SRAM
| 4/2Msmp/ch
| RLE
| custom
| I2C, SPI, UART (SDK)
| $2995-$5500

|- bgcolor="#dddddd"
| [http://www.prologix.biz/ Prologix GPIB-USB/Ethernet controller] ([http://www.sparkfun.com/commerce/product_info.php?products_id=549 S]) (various)
|
|
|
|
|
|
|
|
|

|- bgcolor="#eeeeee"
| [http://www.parallax.com/tabid/768/ProductID/46/Default.aspx Parallax USB-Oscilloscope]
|
|
|
|
|
|
|
|
|

|- bgcolor="#eeeeee"
| [[Saleae Logic]]
| 8
| 0.2-24
|
| Cypress FX2
| none
| none
| Windows (Linux/Mac planned)
| I2C, SPI, UART
| €129.-

|- bgcolor="#eeeeee"
| [http://www.tech-tools.com/dv_dv1.htm TechTools DigiView DV1-100] (various)
|
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [[ZEROPLUS Logic Cube LAP-C]]
| 16
|
|
| ASIC
|
|
|
|
|

|- bgcolor="#6699ff"
| colspan="10" | '''Non-commercial / semi-commercial / hobby projects'''

|- bgcolor="#eeeeee"
| [[Buspirate]]
| 5
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://www.ikalogic.com/scanalogic_home.php ikalogic SCANALOGIC]
|
|
|
|
|
|
|
|
|
|- bgcolor="#dddddd"
| [http://www.ikalogic.com/phpBB3/viewtopic.php?f=17&t=536 ikalogic SCANALOGIC2] (beta)
|
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://minila.sourceforge.net/ miniLA]
| 32
| 100
| 3.3/5
| Xilinx XC95288XL CPLD
| 128Kb/channel
|
|
|
|

|- bgcolor="#dddddd"
| [[Openbench Logic Sniffer]]
| 32
| 200Msps
| 0-5.5
| Xilinx FPGA
| 4K/ch @ 32bit
| RLE
| Java (open, multiple OS)
| I2C, UART
| $45.-

|- bgcolor="#dddddd"
| [http://www.sump.org/projects/analyzer/ Sump]
|
|
|
| FPGA
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://flash-plaice.wikispaces.com/ FLASH - PLAICE]
|
|
|
| FPGA
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://code.google.com/p/cheapla/ cheapla]
|
|
|
| FPGA
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://www.xs4all.nl/~jwasys/old/diy2.html JWA Systems parallel port LA]
|
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://pe1grl.khds.nl/picla/picla.htm picLA]
|
|
|
|
|
|
|
|
|

|}


1 Changeable by replacing input buffers. 
2 External clock up to 16MHz supported. 


TODO:
* http://www.totalphase.com/products/beagle_ism/
* http://mcustore.com/acatalog/PoScope_USB-Based_Oscilloscope.html
* ...

Logic analyzer comparison

2010-05-26T08:40:28Z

Ian:

This is an alphabetically ordered table of various logic analyzer products (commercial and non-commercial) with a short overview of their capabilities. We list all kinds of devices here, not only those supported by sigrok.

You should '''not''' use the information here as the sole source for any buying decisions, this is just meant for informational purposes. Please carefully check the vendor websites if you intend to buy any hardware.

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
!Logic analyzer
!Channels
!Samplerates/MHz
!Voltages/V
!Architecture/chip
!Memory
!Compression
!Vendor software
!Protocol decoders
!Price

|- bgcolor="#6699ff"
| colspan="10" | '''Commercial'''

|- bgcolor="#eeeeee"
| [[ASIX SIGMA]]
| 4/8/16
| 200/100/50
| TTL1
| Spartan-3 + SDRAM
| 256Mbit (56/28/14Msmp/ch)
| RLE
|
| I2C, SPI, UART
| €298.-

|- bgcolor="#dddddd"
| [[Braintechnology USB-LPS]]
| 8/16
| 0.12-24/0.12-122
| 3.3/5
| Cypress FX2
| none
| none
| Windows
| I2C, SPI, UART
| €129.-

|- bgcolor="#eeeeee"
| [[CWAV USBee SX]]
| 8
| 1-24
|
| Cypress FX2
| none
| none
| Windows
| I2C, SPI, UART
| $139.-

|- bgcolor="#dddddd"
| [[Intronix Logicport]]
| 34
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://www.inovaflex.de/logicmaid.html Inovaflex LogicMaid]
|
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://www.nci-usa.com/frame_products_overview.htm NCI GoLogic] (various)
| 36/72
| 250,500 w/o RLE
| cfg.
| Virtex-II + SRAM
| 4/2Msmp/ch
| RLE
| custom
| I2C, SPI, UART (SDK)
| $2995-$5500

|- bgcolor="#dddddd"
| [http://www.prologix.biz/ Prologix GPIB-USB/Ethernet controller] ([http://www.sparkfun.com/commerce/product_info.php?products_id=549 S]) (various)
|
|
|
|
|
|
|
|
|

|- bgcolor="#eeeeee"
| [http://www.parallax.com/tabid/768/ProductID/46/Default.aspx Parallax USB-Oscilloscope]
|
|
|
|
|
|
|
|
|

|- bgcolor="#eeeeee"
| [[Saleae Logic]]
| 8
| 0.2-24
|
| Cypress FX2
| none
| none
| Windows (Linux/Mac planned)
| I2C, SPI, UART
| €129.-

|- bgcolor="#eeeeee"
| [http://www.tech-tools.com/dv_dv1.htm TechTools DigiView DV1-100] (various)
|
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [[ZEROPLUS Logic Cube LAP-C]]
| 16
|
|
| ASIC
|
|
|
|
|

|- bgcolor="#6699ff"
| colspan="10" | '''Non-commercial / semi-commercial / hobby projects'''

|- bgcolor="#eeeeee"
| [[Buspirate]]
| 5
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://www.ikalogic.com/scanalogic_home.php ikalogic SCANALOGIC]
|
|
|
|
|
|
|
|
|
|- bgcolor="#dddddd"
| [http://www.ikalogic.com/phpBB3/viewtopic.php?f=17&t=536 ikalogic SCANALOGIC2] (beta)
|
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://minila.sourceforge.net/ miniLA]
| 32
| 100
| 3.3/5
| Xilinx XC95288XL CPLD
| 128Kb/channel
|
|
|
|

|- bgcolor="#dddddd"
| [[Openbench Logic Sniffer]]
| 32
| 200
| 0-5.5
| Xilinx FPGA
| 4K/ch @ 32bit
| RLE
| Java (multiple platforms)
| I2C, UART
| $45.-

|- bgcolor="#dddddd"
| [http://www.sump.org/projects/analyzer/ Sump]
|
|
|
| FPGA
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://flash-plaice.wikispaces.com/ FLASH - PLAICE]
|
|
|
| FPGA
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://code.google.com/p/cheapla/ cheapla]
|
|
|
| FPGA
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://www.xs4all.nl/~jwasys/old/diy2.html JWA Systems parallel port LA]
|
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://pe1grl.khds.nl/picla/picla.htm picLA]
|
|
|
|
|
|
|
|
|

|}


1 Changeable by replacing input buffers. 
2 External clock up to 16MHz supported. 


TODO:
* http://www.totalphase.com/products/beagle_ism/
* http://mcustore.com/acatalog/PoScope_USB-Based_Oscilloscope.html
* ...

Logic analyzer comparison

2010-05-26T08:39:45Z

Ian:

This is an alphabetically ordered table of various logic analyzer products (commercial and non-commercial) with a short overview of their capabilities. We list all kinds of devices here, not only those supported by sigrok.

You should '''not''' use the information here as the sole source for any buying decisions, this is just meant for informational purposes. Please carefully check the vendor websites if you intend to buy any hardware.

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
!Logic analyzer
!Channels
!Samplerates/MHz
!Voltages/V
!Architecture/chip
!Memory
!Compression
!Vendor software
!Protocol decoders
!Price

|- bgcolor="#6699ff"
| colspan="10" | '''Commercial'''

|- bgcolor="#eeeeee"
| [[ASIX SIGMA]]
| 4/8/16
| 200/100/50
| TTL1
| Spartan-3 + SDRAM
| 256Mbit (56/28/14Msmp/ch)
| RLE
|
| I2C, SPI, UART
| €298.-

|- bgcolor="#dddddd"
| [[Braintechnology USB-LPS]]
| 8/16
| 0.12-24/0.12-122
| 3.3/5
| Cypress FX2
| none
| none
| Windows
| I2C, SPI, UART
| €129.-

|- bgcolor="#eeeeee"
| [[CWAV USBee SX]]
| 8
| 1-24
|
| Cypress FX2
| none
| none
| Windows
| I2C, SPI, UART
| $139.-

|- bgcolor="#dddddd"
| [[Intronix Logicport]]
| 34
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://www.inovaflex.de/logicmaid.html Inovaflex LogicMaid]
|
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://www.nci-usa.com/frame_products_overview.htm NCI GoLogic] (various)
| 36/72
| 250,500 w/o RLE
| cfg.
| Virtex-II + SRAM
| 4/2Msmp/ch
| RLE
| custom
| I2C, SPI, UART (SDK)
| $2995-$5500

|- bgcolor="#dddddd"
| [http://www.prologix.biz/ Prologix GPIB-USB/Ethernet controller] ([http://www.sparkfun.com/commerce/product_info.php?products_id=549 S]) (various)
|
|
|
|
|
|
|
|
|

|- bgcolor="#eeeeee"
| [http://www.parallax.com/tabid/768/ProductID/46/Default.aspx Parallax USB-Oscilloscope]
|
|
|
|
|
|
|
|
|

|- bgcolor="#eeeeee"
| [[Saleae Logic]]
| 8
| 0.2-24
|
| Cypress FX2
| none
| none
| Windows (Linux/Mac planned)
| I2C, SPI, UART
| €129.-

|- bgcolor="#eeeeee"
| [http://www.tech-tools.com/dv_dv1.htm TechTools DigiView DV1-100] (various)
|
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [[ZEROPLUS Logic Cube LAP-C]]
| 16
|
|
| ASIC
|
|
|
|
|

|- bgcolor="#6699ff"
| colspan="10" | '''Non-commercial / semi-commercial / hobby projects'''

|- bgcolor="#eeeeee"
| [[Buspirate]]
| 5
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://www.ikalogic.com/scanalogic_home.php ikalogic SCANALOGIC]
|
|
|
|
|
|
|
|
|
|- bgcolor="#dddddd"
| [http://www.ikalogic.com/phpBB3/viewtopic.php?f=17&t=536 ikalogic SCANALOGIC2] (beta)
|
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://minila.sourceforge.net/ miniLA]
| 32
| 100
| 3.3/5
| Xilinx XC95288XL CPLD
| 128Kb/channel
|
|
|
|

|- bgcolor="#dddddd"
| [[Openbench Logic Sniffer]]
| 32
| 200
| 0-5.5
| Xilinx FPGA
| 4K/ch @ 32bit
| RLE
| Java (multiple platforms)
| I2C, UART
| $45

|- bgcolor="#dddddd"
| [http://www.sump.org/projects/analyzer/ Sump]
|
|
|
| FPGA
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://flash-plaice.wikispaces.com/ FLASH - PLAICE]
|
|
|
| FPGA
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://code.google.com/p/cheapla/ cheapla]
|
|
|
| FPGA
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://www.xs4all.nl/~jwasys/old/diy2.html JWA Systems parallel port LA]
|
|
|
|
|
|
|
|
|

|- bgcolor="#dddddd"
| [http://pe1grl.khds.nl/picla/picla.htm picLA]
|
|
|
|
|
|
|
|
|

|}


1 Changeable by replacing input buffers. 
2 External clock up to 16MHz supported. 


TODO:
* http://www.totalphase.com/products/beagle_ism/
* http://mcustore.com/acatalog/PoScope_USB-Based_Oscilloscope.html
* ...

Openbench Logic Sniffer

2010-05-26T08:37:09Z

Ian:

[[File:Openbench logic sniffer front.jpg|thumb|right|Openbench Logic Sniffer]]
[[File:Openbench logic sniffer back.jpg|thumb|right|Openbench Logic Sniffer, back]]

The [http://www.gadgetfactory.net/gf/project/butterflylogic/ Openbench Logic Sniffer] (OLS) is an FPGA-based logic analyzer, supporting 32 probes for probing up to 100MHz signals and advanced trigger functionality. It is a fully open source device — the circuit design, VHDL code for the FPGA, firmware for the PIC microcontroller and Java-based client software are all freely available. The project is a collaboration between [http://www.gadgetfactory.net/ Gadget Factory] and [http://dangerousprototypes.com/ Dangerous Prototypes].

The device started life as the [http://www.sump.org/projects/analyzer/ Sump Logic Analyzer], which was meant to be run on a Digilent FPGA development board. The Openbench Logic Analyzer unit is a custom-designed board with low cost in mind: it can be bought for $45 from [http://www.seeedstudio.com/depot/preorder-open-workbench-logic-sniffer-p-612.html?cPath=61_76 Seeed Studio].

Communication between the board and the PC is done via a USB port connected to a PIC 18F24J50 microcontroller, which presents a standard USB ACM profile. The host handles this as a serial port. The default maximum serial speed of the SUMP Java client is 115200bps, but the USB ACM virtual serial port can be opened at much higher speeds. An overview of the endpoint profile is at [[Openbench Logic Sniffer/Info]].

== Status ==

The sigrok driver does not currently support the "serial" trigger mode. This allows a single trigger to be set (on one or more probes), but with up to 32 stages. The parallel mode is supported, which supports up to 4 distinct trigger stages on any probe.

Using an external clock is not yet supported. Also the 200MHz mode will not work right now, since the driver always expects 32-bit sample values.

RLE mode is supported but currently unused, so there is no compression for now. This needs to depend on which version of the FPGA software is detected; the original Sump didn't have RLE.

== Communications Protocol ==

The communications protocol between the board and the PC is below, taken from the [http://www.sump.org/projects/analyzer/protocol/ original Sump documentation].

All communication is done using a standard RS232 connection with 8 data bits, 1 stop bit and no parity. The transfer rate is not emulated over USB and can be set to any speed supported by the operating system. Pump-loader, an update utility for the Logic Sniffer ROM chip, uses 921600bps by default. XON/XOFF software flow control is available.

When sending captured data the analyzer will send blocks of four bytes, the first containing the lowest channels. No start or end sequence exists. The host can assume an end of transmission if no data has been received for the duration of one byte.

The protocol used by hardware version 0.5 and older is not covered here. Hardware 0.6 uses protocol version 0, and hardware 0.7 uses protocol version 1. Unless otherwise stated, commands exist in both versions.

The following list provides a short overview of commands understood by the analyzer.

=== Short Commands ===

These commands are exactly one byte long.

'''Reset (0x00)'''
: Resets the device. Should be sent 5 times when the receiver status is unknown. (It could be waiting for up to four bytes of pending long command data.)

'''Run (0x01)'''
: Arms the trigger.

'''ID (0x02)'''
: Asks for device identification. The device will respond with four bytes. The first three ("SLA") identify the device. The last one identifies the protocol version which is currently either "0" or "1".

'''XON (0x11)'''
: Put transmitter out of pause mode. It will continue to transmit captured data if any is pending. This command is being used for xon/xoff flow control.

'''XOFF (0x13)'''
: Put transmitter in pause mode. It will stop transmitting captured data. This command is being used for xon/xoff flow control.

=== Long Commands ===

Are five bytes long. The first byte contains the opcode. The bytes are displayed in the order in which they are sent to the serial port starting left. The bits within one byte are displayed most significant first.

'''Set Trigger Mask (0xc0, 0xc4, 0xc8, 0xcc)'''
: Defines which trigger values must match. In parallel mode each bit represents one channel, in serial mode each bit represents one of the last 32 samples of the selected channel. The opcodes refer to stage 0-3 in the order given above. (Protocol version 0 only supports stage 0.)
: [[Image:1100xx00.png]]

'''Set Trigger Values (0xc1, 0xc5, 0xc9, 0xcd)'''
: Defines which values individual bits must have. In parallel mode each bit represents one channel, in serial mode each bit represents one of the last 32 samples of the selected channel. The opcodes refer to stage 0-3 in the order given above. (Protocol version 0 only supports stage 0.)
: [[Image:1100xx01.png]]

'''Set Trigger Configuration (0xc2, 0xc6, 0xca, 0xce)'''
: Configures the selected trigger stage. The opcodes refer to stage 0-3 in the order given above. The following parameters will be set:

:: '''delay'''
::: If a match occures, the action of the stage is delayed by the given number of samples.
:: '''level'''
::: Trigger level at which the stage becomes active.
:: '''channel'''
::: Channel to be used in serial mode. (0-31 in normal operation; 0-15 when demux flag is set)
:: '''serial'''
::: When set to 1 the stage operates as serial trigger, otherwise it used as parallel trigger.
:: '''start'''
::: When set to 1 a match will start the capturing process. The trigger level will rise on match regardless of this flag. (Command available as of protocol version 1.)

: [[Image:1100xx10.png]]

'''Set Divider (0x80)'''
: When x is written, the sampling frequency is set to f = clock / (x + 1).

: [[Image:10000000.png]]

'''Set Read & Delay Count (0x81)'''
: Read Count is the number of samples (divided by four) to read back from memory and sent to the host computer. Delay Count is the number of samples (divided by four) to capture after the trigger fired. A Read Count bigger than the Delay Count means that data from before the trigger match will be read back. This data will only be valid if the device was running long enough before the trigger matched.
: [[Image:10000001.png]]

'''Set Flags (0x82)'''
: Sets the following flags:

:: '''demux'''
::: Enables the demux input module. (Filter must be off.)
:: '''filter'''
::: Enables the filter input module. (Demux must be off.)
:: '''channel groups'''
::: Disable channel group. Disabled groups are excluded from data transmissions. This can be used to speed up transfers. There are four groups, each represented by one bit. Starting with the least significant bit of the channel group field channels are assigned as follows: 0-7, 8-15, 16-23, 24-31.
:: '''external'''
::: Selects the clock to be used for sampling. If set to 0, the internal clock divided by the configured divider is used, and if set to 1, the external clock will be used. Filter and demux are only available with internal clock.
:: '''inverted'''
::: When set to 1, the external clock will be inverted before being used. The inversion causes a delay that may cause problems at very high clock rates. This option only has an effect with external set to 1.

: [[Image:10000010.png]]

Openbench Logic Sniffer

2010-05-26T08:34:45Z

Ian:

[[File:Openbench logic sniffer front.jpg|thumb|right|Openbench Logic Sniffer]]
[[File:Openbench logic sniffer back.jpg|thumb|right|Openbench Logic Sniffer, back]]

The [http://www.gadgetfactory.net/gf/project/butterflylogic/ Openbench Logic Sniffer] (OLS) is an FPGA-based logic analyzer, supporting 32 probes for probing up to 100MHz signals and advanced trigger functionality. It is a fully open source device — the circuit design, VHDL code for the FPGA, firmware for the PIC microcontroller and Java-based client software are all freely available. The project is a collaboration between [http://www.gadgetfactory.net/ Gadget Factory] and [http://dangerousprototypes.com/ Dangerous Prototypes].

The device started life as the [http://www.sump.org/projects/analyzer/ Sump Logic Analyzer], which was meant to be run on a Digilent FPGA development board. The Openbench Logic Analyzer unit is a custom-designed board with low cost in mind: it can be bought for $45 from [http://www.seeedstudio.com/depot/preorder-open-workbench-logic-sniffer-p-612.html?cPath=61_76 Seeed Studio].

Communication between the board and the PC is done via a USB port connected to a PIC 18F24J50 microcontroller, which presents a standard USB ACM profile. The host handles this as a serial port. The default maximum serial speed of the SUMP Java client is 115200bps, but the USB ACM virtual serial port can be opened at much higher speeds. An overview of the endpoint profile is at [[Openbench Logic Sniffer/Info]].

== Status ==

The sigrok driver does not currently support the "serial" trigger mode. This allows a single trigger to be set (on one or more probes), but with up to 32 stages. The parallel mode is supported, which supports up to 4 distinct trigger stages on any probe.

Using an external clock is not yet supported. Also the 200MHz mode will not work right now, since the driver always expects 32-bit sample values.

RLE mode is supported but currently unused, so there is no compression for now. This needs to depend on which version of the FPGA software is detected; the original Sump didn't have RLE.

== Communications Protocol ==

The communications protocol between the board and the PC is below, taken from the [http://www.sump.org/projects/analyzer/protocol/ original Sump documentation].

All communication is done using a standard RS232 connection with 8 data bits, 1 stop bit and no parity. The transfer rate can be set to 115200, 57600, 38400 or 19200 bps. XON/XOFF software flow control is available.

When sending captured data the analyzer will send blocks of four bytes, the first containing the lowest channels. No start or end sequence exists. The host can assume an end of transmission if no data has been received for the duration of one byte.

The protocol used by hardware version 0.5 and older is not covered here. Hardware 0.6 uses protocol version 0, and hardware 0.7 uses protocol version 1. Unless otherwise stated, commands exist in both versions.

The following list provides a short overview of commands understood by the analyzer.

=== Short Commands ===

These commands are exactly one byte long.

'''Reset (0x00)'''
: Resets the device. Should be sent 5 times when the receiver status is unknown. (It could be waiting for up to four bytes of pending long command data.)

'''Run (0x01)'''
: Arms the trigger.

'''ID (0x02)'''
: Asks for device identification. The device will respond with four bytes. The first three ("SLA") identify the device. The last one identifies the protocol version which is currently either "0" or "1".

'''XON (0x11)'''
: Put transmitter out of pause mode. It will continue to transmit captured data if any is pending. This command is being used for xon/xoff flow control.

'''XOFF (0x13)'''
: Put transmitter in pause mode. It will stop transmitting captured data. This command is being used for xon/xoff flow control.

=== Long Commands ===

Are five bytes long. The first byte contains the opcode. The bytes are displayed in the order in which they are sent to the serial port starting left. The bits within one byte are displayed most significant first.

'''Set Trigger Mask (0xc0, 0xc4, 0xc8, 0xcc)'''
: Defines which trigger values must match. In parallel mode each bit represents one channel, in serial mode each bit represents one of the last 32 samples of the selected channel. The opcodes refer to stage 0-3 in the order given above. (Protocol version 0 only supports stage 0.)
: [[Image:1100xx00.png]]

'''Set Trigger Values (0xc1, 0xc5, 0xc9, 0xcd)'''
: Defines which values individual bits must have. In parallel mode each bit represents one channel, in serial mode each bit represents one of the last 32 samples of the selected channel. The opcodes refer to stage 0-3 in the order given above. (Protocol version 0 only supports stage 0.)
: [[Image:1100xx01.png]]

'''Set Trigger Configuration (0xc2, 0xc6, 0xca, 0xce)'''
: Configures the selected trigger stage. The opcodes refer to stage 0-3 in the order given above. The following parameters will be set:

:: '''delay'''
::: If a match occures, the action of the stage is delayed by the given number of samples.
:: '''level'''
::: Trigger level at which the stage becomes active.
:: '''channel'''
::: Channel to be used in serial mode. (0-31 in normal operation; 0-15 when demux flag is set)
:: '''serial'''
::: When set to 1 the stage operates as serial trigger, otherwise it used as parallel trigger.
:: '''start'''
::: When set to 1 a match will start the capturing process. The trigger level will rise on match regardless of this flag. (Command available as of protocol version 1.)

: [[Image:1100xx10.png]]

'''Set Divider (0x80)'''
: When x is written, the sampling frequency is set to f = clock / (x + 1).

: [[Image:10000000.png]]

'''Set Read & Delay Count (0x81)'''
: Read Count is the number of samples (divided by four) to read back from memory and sent to the host computer. Delay Count is the number of samples (divided by four) to capture after the trigger fired. A Read Count bigger than the Delay Count means that data from before the trigger match will be read back. This data will only be valid if the device was running long enough before the trigger matched.
: [[Image:10000001.png]]

'''Set Flags (0x82)'''
: Sets the following flags:

:: '''demux'''
::: Enables the demux input module. (Filter must be off.)
:: '''filter'''
::: Enables the filter input module. (Demux must be off.)
:: '''channel groups'''
::: Disable channel group. Disabled groups are excluded from data transmissions. This can be used to speed up transfers. There are four groups, each represented by one bit. Starting with the least significant bit of the channel group field channels are assigned as follows: 0-7, 8-15, 16-23, 24-31.
:: '''external'''
::: Selects the clock to be used for sampling. If set to 0, the internal clock divided by the configured divider is used, and if set to 1, the external clock will be used. Filter and demux are only available with internal clock.
:: '''inverted'''
::: When set to 1, the external clock will be inverted before being used. The inversion causes a delay that may cause problems at very high clock rates. This option only has an effect with external set to 1.

: [[Image:10000010.png]]