sigrok - User contributions [en]

ASIX OMEGA

2016-11-04T21:05:34Z

Cezar: /* Photos */

The ASIX OMEGA is new version of [[ASIX SIGMA]] logic analyzer. It is a 16 channel logic analyzer with sample rate support up to 400 MHz and with 512 Mbit on-board memory. It uses Huffman compression and achieves much better compression ratio than SIGMA. Two or more OMEGA analyzers can be connected in with synchronization cable and use more inputs.

[[Category:Device]]
[[Category:Logic analyzer]]

{{Infobox logic analyzer
| image = [[File:ASIX Omega.png|180px]]
| name = ASIX Omega
| status = in progress
| source_code_dir = asix-sigma
| channels = 16
| samplerate = 400MHz @ 8ch, 200MHz @ 16
| samplerate_state = ?
| triggers = value, edge, duration, sequence, counter, logical ops
| voltages = -0.3V — 5.5V
| threshold = Fixed: VIH=2.0V, VIL=0.8V (suitable for TTL, LVTTL, 2.7-5.5V CMOS)
| memory = 512 megabit
| compression = "real-time hardware data compression"
| website = [http://www.asix.net/dbg_omega.htm asix.net]
}}

The '''ASIX OMEGA''' is a USB-based, 16-channel logic analyzer with up to 400MHz sampling rate.

See [[ASIX OMEGA/Info]] for more details (such as '''lsusb -vvv''' output) about the device.

== Hardware ==

* Xilinx Spartan [http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf XC3S200A]
* FTDI [http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232H.pdf FT232HL]
* 2 x NXP [http://www.nxp.com/documents/data_sheet/74LVC_LVCH245A.pdf LVC245A]
* 2 x [https://www.micron.com/~/media/documents/products/data-sheet/dram/256mb_sdr.pdf MT48LC16M16A2B4-7E]
* [https://www.idt.com/document/dst/570-datasheet ICS570BL]
* [http://www.ti.com/lit/ds/symlink/sn65mlvd204a.pdf MF204A]
* [http://www.ti.com/lit/ds/scas290q/scas290q.pdf LC125A]
* ...

== Photos ==
<gallery>
File:ASIX_Omega.png
File:Omega-Top.jpg
File:Omega-Bottom.jpg
</gallery>

== Documentation ==

TODO

== Example usage ==

TODO

== Firmware ==

TODO

== Resources ==

TODO

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:In progress]]

ASIX OMEGA

2016-11-04T20:46:03Z

Cezar: /* Photos */

The ASIX OMEGA is new version of [[ASIX SIGMA]] logic analyzer. It is a 16 channel logic analyzer with sample rate support up to 400 MHz and with 512 Mbit on-board memory. It uses Huffman compression and achieves much better compression ratio than SIGMA. Two or more OMEGA analyzers can be connected in with synchronization cable and use more inputs.

[[Category:Device]]
[[Category:Logic analyzer]]

{{Infobox logic analyzer
| image = [[File:ASIX Omega.png|180px]]
| name = ASIX Omega
| status = in progress
| source_code_dir = asix-sigma
| channels = 16
| samplerate = 400MHz @ 8ch, 200MHz @ 16
| samplerate_state = ?
| triggers = value, edge, duration, sequence, counter, logical ops
| voltages = -0.3V — 5.5V
| threshold = Fixed: VIH=2.0V, VIL=0.8V (suitable for TTL, LVTTL, 2.7-5.5V CMOS)
| memory = 512 megabit
| compression = "real-time hardware data compression"
| website = [http://www.asix.net/dbg_omega.htm asix.net]
}}

The '''ASIX OMEGA''' is a USB-based, 16-channel logic analyzer with up to 400MHz sampling rate.

See [[ASIX OMEGA/Info]] for more details (such as '''lsusb -vvv''' output) about the device.

== Hardware ==

* Xilinx Spartan [http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf XC3S200A]
* FTDI [http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232H.pdf FT232HL]
* 2 x NXP [http://www.nxp.com/documents/data_sheet/74LVC_LVCH245A.pdf LVC245A]
* 2 x [https://www.micron.com/~/media/documents/products/data-sheet/dram/256mb_sdr.pdf MT48LC16M16A2B4-7E]
* [https://www.idt.com/document/dst/570-datasheet ICS570BL]
* [http://www.ti.com/lit/ds/symlink/sn65mlvd204a.pdf MF204A]
* [http://www.ti.com/lit/ds/scas290q/scas290q.pdf LC125A]
* ...

== Photos ==
<gallery>
File:Omega-Top.jpg
File:Omega-Bottom.jpg
</gallery>

== Documentation ==

TODO

== Example usage ==

TODO

== Firmware ==

TODO

== Resources ==

TODO

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:In progress]]

ASIX SIGMA / SIGMA2

2016-11-04T20:45:00Z

Cezar: Undo revision 11991 by Cezar (talk)

{{Infobox logic analyzer
| image = [[File:ASIX SIGMA 2.png|180px]]
| name = ASIX SIGMA / SIGMA2
| status = supported
| source_code_dir = asix-sigma
| channels = 16
| samplerate = 200MHz @ 4ch, 100MHz @ 8ch, 50MHz @ 16ch
| samplerate_state = 50MHz
| triggers = value, edge, duration, sequence, counter, logical ops
| voltages = -0.3V — 5.5V
| threshold = Fixed: VIH=2.0V, VIL=0.8V (suitable for TTL, LVTTL, 2.7-5.5V CMOS)
| memory = 32MByte (SDRAM)
| compression = "real-time hardware data compression"
| website = [http://tools.asix.net/dbg_sigma.htm asix.net]
}}

The '''ASIX SIGMA/SIGMA2''' is a USB-based, 16-channel logic analyzer with up to 200MHz sampling rate.

See [[ASIX SIGMA/Info]] for more details (such as '''lsusb -vvv''' output) about the device.


Many thanks to the vendor ([http://www.asix.net/ ASIX]) for providing information on the protocol used to communicate with the device and for releasing the device's firmware / FPGA bitstreams under a [http://sigrok.org/gitweb/?p=sigrok-firmware.git;a=blob;f=asix-sigma/LICENSE.Sigma license which allows us to distribute the files].


== Hardware ==

* Xilinx Spartan XC3S50
* FTDI FT245RL
* 2x TI SN74LVC245AN
* MT 48LCI6MI6A2
* ...

== Photos ==

=== ASIX SIGMA ===
<gallery>
File:ASIX SIGMA.jpg
File:Sigma.jpg
</gallery>
=== ASIX SIGMA 2 ===
<gallery>
File:ASIX SIGMA 2 back.jpg
File:ASIX SIGMA 2 USB.jpg
File:ASIX SIGMA 2 header.jpg
File:ASIX SIGMA 2 PCB top.jpg
File:ASIX SIGMA 2 PCB bottom.jpg
</gallery>

== Documentation ==

The ASIX SIGMA/SIGMA2 firmware files are generously provided by the vendor for distribution. As a result, the device works out of the box with sigrok. Trigger support has been implemented in 100MHz and 200MHz modes for rising/falling edges. In other modes, users can specify additional trigger values, listed in the table below.

NOTE: In 50MHz mode, the device uses an internal 8-bit integer divider. The sample rate is therefore 50MHz/n , where n = 1...256 . The table below matches sigrok's current representation and will need to be changed.

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
!Samplerate
!Number of probes
!Trigger support
|- bgcolor="#eeeeee"
| 200 kHz
| 16
| Edge of two probes, state, boolean expression1
|- bgcolor="#dddddd"
| 250 kHz
| 16
| Edge of two probes, state, boolean expression1
|- bgcolor="#eeeeee"
| 500 kHz
| 16
| Edge of two probes, state, boolean expression1
|- bgcolor="#dddddd"
| 1 MHz
| 16
| Edge of two probes, state, boolean expression1
|- bgcolor="#eeeeee"
| 5 MHz
| 16
| Edge of two probes, state, boolean expression1
|- bgcolor="#dddddd"
| 10 MHz
| 16
| Edge of two probes, state, boolean expression1
|- bgcolor="#eeeeee"
| 25 MHz
| 16
| Edge of two probes, state, boolean expression1
|- bgcolor="#dddddd"
| 50 MHz
| 16
| Edge of two probes, state, boolean expression1
|- bgcolor="#eeeeee"
| 100 MHz
| 8
| Edge of one probe
|- bgcolor="#dddddd"
| 200 MHz
| 4
| Edge of one probe
|}


1 Boolean expression feature not implemented in sigrok yet. 


== Example usage ==

An example that captures from 4 probes, for 100ms at 10MHz, with trigger condition 1:high, 2:rising, 3:low, 4:high.

$ '''sigrok-cli --driver asix-sigma --config samplerate=10m --wait-trigger \'''
'''--triggers 1=1,2=r,3=0,4=1 --output-format bits --probes 1-4 --time 100ms'''

== Firmware ==

The firmware files (FPGA bitstreams) for the ASIX SIGMA/SIGMA2 have been provided by the vendor under a [http://sigrok.org/gitweb/?p=sigrok-firmware.git;a=blob;f=asix-sigma/LICENSE.Sigma license which allows redistribution], and are available from the [http://sigrok.org/gitweb/?p=sigrok-firmware.git sigrok-firmware] repository. See [[Firmware]] for installation instructions.

== Differences between SIGMA and SIGMA2 ==

The hardware of SIGMA and SIGMA2 is almost identical, up to few exceptions:

* Seven one-color LEDs were replaced with two two-color LEDs.
* A button was added. It can be used to start, stop, trigger.
* The SIGMA has input TTLs in DIL sockets, SIGMA2 is has input TTLs in SMD package.

The new hardware revision requires the new firmware files to support the button and the different LED wiring. The new firmware is usable for both SIGMA '''and''' SIGMA2. However, the new hardware revision cannot work with the old firmware files.

== Resources ==

* [http://labs.ping.uio.no/2010/04/initial-support-for-asix-sigma-in-sigrok/ Initial support for Asix Sigma in Sigrok]
* [http://labs.ping.uio.no/2009/09/sampi-a-logic-analyzer/ PING Labs: Sampi – A Logic Analyzer]
* [http://www.flickr.com/photos/chlunde/3383669140/ flickr: ASIX SIGMA in chlunde's photostream] (photos and more information about the device)

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Supported]]

ASIX SIGMA / SIGMA2

2016-11-04T20:43:47Z

Cezar: /* ASIX Omega */

{{Infobox logic analyzer
| image = [[File:ASIX SIGMA 2.png|180px]]
| name = ASIX SIGMA / SIGMA2
| status = supported
| source_code_dir = asix-sigma
| channels = 16
| samplerate = 200MHz @ 4ch, 100MHz @ 8ch, 50MHz @ 16ch
| samplerate_state = 50MHz
| triggers = value, edge, duration, sequence, counter, logical ops
| voltages = -0.3V — 5.5V
| threshold = Fixed: VIH=2.0V, VIL=0.8V (suitable for TTL, LVTTL, 2.7-5.5V CMOS)
| memory = 32MByte (SDRAM)
| compression = "real-time hardware data compression"
| website = [http://tools.asix.net/dbg_sigma.htm asix.net]
}}

The '''ASIX SIGMA/SIGMA2''' is a USB-based, 16-channel logic analyzer with up to 200MHz sampling rate.

See [[ASIX SIGMA/Info]] for more details (such as '''lsusb -vvv''' output) about the device.


Many thanks to the vendor ([http://www.asix.net/ ASIX]) for providing information on the protocol used to communicate with the device and for releasing the device's firmware / FPGA bitstreams under a [http://sigrok.org/gitweb/?p=sigrok-firmware.git;a=blob;f=asix-sigma/LICENSE.Sigma license which allows us to distribute the files].


== Hardware ==

* Xilinx Spartan XC3S50
* FTDI FT245RL
* 2x TI SN74LVC245AN
* MT 48LCI6MI6A2
* ...

== Photos ==

=== ASIX SIGMA ===
<gallery>
File:ASIX SIGMA.jpg
File:Sigma.jpg
</gallery>
=== ASIX SIGMA 2 ===
<gallery>
File:Omega-Top.jpg
File:Omega-Bottom.jpg
</gallery>

== Documentation ==

The ASIX SIGMA/SIGMA2 firmware files are generously provided by the vendor for distribution. As a result, the device works out of the box with sigrok. Trigger support has been implemented in 100MHz and 200MHz modes for rising/falling edges. In other modes, users can specify additional trigger values, listed in the table below.

NOTE: In 50MHz mode, the device uses an internal 8-bit integer divider. The sample rate is therefore 50MHz/n , where n = 1...256 . The table below matches sigrok's current representation and will need to be changed.

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
!Samplerate
!Number of probes
!Trigger support
|- bgcolor="#eeeeee"
| 200 kHz
| 16
| Edge of two probes, state, boolean expression1
|- bgcolor="#dddddd"
| 250 kHz
| 16
| Edge of two probes, state, boolean expression1
|- bgcolor="#eeeeee"
| 500 kHz
| 16
| Edge of two probes, state, boolean expression1
|- bgcolor="#dddddd"
| 1 MHz
| 16
| Edge of two probes, state, boolean expression1
|- bgcolor="#eeeeee"
| 5 MHz
| 16
| Edge of two probes, state, boolean expression1
|- bgcolor="#dddddd"
| 10 MHz
| 16
| Edge of two probes, state, boolean expression1
|- bgcolor="#eeeeee"
| 25 MHz
| 16
| Edge of two probes, state, boolean expression1
|- bgcolor="#dddddd"
| 50 MHz
| 16
| Edge of two probes, state, boolean expression1
|- bgcolor="#eeeeee"
| 100 MHz
| 8
| Edge of one probe
|- bgcolor="#dddddd"
| 200 MHz
| 4
| Edge of one probe
|}


1 Boolean expression feature not implemented in sigrok yet. 


== Example usage ==

An example that captures from 4 probes, for 100ms at 10MHz, with trigger condition 1:high, 2:rising, 3:low, 4:high.

$ '''sigrok-cli --driver asix-sigma --config samplerate=10m --wait-trigger \'''
'''--triggers 1=1,2=r,3=0,4=1 --output-format bits --probes 1-4 --time 100ms'''

== Firmware ==

The firmware files (FPGA bitstreams) for the ASIX SIGMA/SIGMA2 have been provided by the vendor under a [http://sigrok.org/gitweb/?p=sigrok-firmware.git;a=blob;f=asix-sigma/LICENSE.Sigma license which allows redistribution], and are available from the [http://sigrok.org/gitweb/?p=sigrok-firmware.git sigrok-firmware] repository. See [[Firmware]] for installation instructions.

== Differences between SIGMA and SIGMA2 ==

The hardware of SIGMA and SIGMA2 is almost identical, up to few exceptions:

* Seven one-color LEDs were replaced with two two-color LEDs.
* A button was added. It can be used to start, stop, trigger.
* The SIGMA has input TTLs in DIL sockets, SIGMA2 is has input TTLs in SMD package.

The new hardware revision requires the new firmware files to support the button and the different LED wiring. The new firmware is usable for both SIGMA '''and''' SIGMA2. However, the new hardware revision cannot work with the old firmware files.

== Resources ==

* [http://labs.ping.uio.no/2010/04/initial-support-for-asix-sigma-in-sigrok/ Initial support for Asix Sigma in Sigrok]
* [http://labs.ping.uio.no/2009/09/sampi-a-logic-analyzer/ PING Labs: Sampi – A Logic Analyzer]
* [http://www.flickr.com/photos/chlunde/3383669140/ flickr: ASIX SIGMA in chlunde's photostream] (photos and more information about the device)

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Supported]]

File:Omega-Top.jpg

2016-11-04T20:41:15Z

Cezar: ASIX Omega Logic analyzer board: top

== Summary ==
ASIX Omega Logic analyzer board: top
== Licensing ==
{{PD}}

File:Omega-Bottom.jpg

2016-11-04T20:40:47Z

Cezar: ASIX Omega Logic analyzer board: bottom

== Summary ==
ASIX Omega Logic analyzer board: bottom
== Licensing ==
{{PD}}

ASIX OMEGA

2016-11-04T20:30:51Z

Cezar: /* Hardware */

The ASIX OMEGA is new version of [[ASIX SIGMA]] logic analyzer. It is a 16 channel logic analyzer with sample rate support up to 400 MHz and with 512 Mbit on-board memory. It uses Huffman compression and achieves much better compression ratio than SIGMA. Two or more OMEGA analyzers can be connected in with synchronization cable and use more inputs.

[[Category:Device]]
[[Category:Logic analyzer]]

{{Infobox logic analyzer
| image = [[File:ASIX Omega.png|180px]]
| name = ASIX Omega
| status = in progress
| source_code_dir = asix-sigma
| channels = 16
| samplerate = 400MHz @ 8ch, 200MHz @ 16
| samplerate_state = ?
| triggers = value, edge, duration, sequence, counter, logical ops
| voltages = -0.3V — 5.5V
| threshold = Fixed: VIH=2.0V, VIL=0.8V (suitable for TTL, LVTTL, 2.7-5.5V CMOS)
| memory = 512 megabit
| compression = "real-time hardware data compression"
| website = [http://www.asix.net/dbg_omega.htm asix.net]
}}

The '''ASIX OMEGA''' is a USB-based, 16-channel logic analyzer with up to 400MHz sampling rate.

See [[ASIX OMEGA/Info]] for more details (such as '''lsusb -vvv''' output) about the device.

== Hardware ==

* Xilinx Spartan [http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf XC3S200A]
* FTDI [http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232H.pdf FT232HL]
* 2 x NXP [http://www.nxp.com/documents/data_sheet/74LVC_LVCH245A.pdf LVC245A]
* 2 x [https://www.micron.com/~/media/documents/products/data-sheet/dram/256mb_sdr.pdf MT48LC16M16A2B4-7E]
* [https://www.idt.com/document/dst/570-datasheet ICS570BL]
* [http://www.ti.com/lit/ds/symlink/sn65mlvd204a.pdf MF204A]
* [http://www.ti.com/lit/ds/scas290q/scas290q.pdf LC125A]
* ...

== Photos ==

TODO

== Documentation ==

TODO

== Example usage ==

TODO

== Firmware ==

TODO

== Resources ==

TODO

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:In progress]]